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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
FEATURES
* 15 single ended LVCMOS outputs, 7 typical output impedance * Selectable LVCMOS or LVPECL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 160MHz * Output skew: 350ps (maximum) * Part-to-part skew: 2.75ns (maximum) * 3.3V supply voltage * -40C to 85C ambient operating temperature * Pin compatible to the MPC949
ICS87949I
GENERAL DESCRIPTION
The ICS87949I is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM family HiPerClockSTM of High Performance Clock Solutions from ICS. The ICS87949I has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949I is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS87949I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC 0 QD0:QD5 1 DIV_SELD MR/nOE 0 0 1 1 /1 /2 R 0 QA0:QA1
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2 nc
MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
nc GND QC0 VDDC QC1 GND QC2 VDDC QC3 GND GND QD5 nc
ICS87949I
33 32 31 30 29 28
10 11 12
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
nc GND QD0 VDDD QD1 GND QD2 VDDD QD3 GND QD4 VDDD nc
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View
87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
Type Input Input Power Input Input Input Input Input Input Input Input Power Unused Output Power Output Power Power Output Output Power Description Master reset and output enable When LOW, output drivers are Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Core supply pin. Pullup Pullup LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input.
ICS87949I
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 5 6 7 8 9 10 11 12 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 14, 26, 27, 39, 40 16, 18, 20, 22, 24, 28 17, 21, 25 31, 33, 35, 37 32, 36 41, 45 42, 44, 46 49, 51 50 Name MR/nOE CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND nc QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Pulldown Non-inver ting differential LVPECL clock input. Pulldown PCLK select input. LVCMOS / LVTTL interface levels. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. No connect. Bank D outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Bank A outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
Test Conditions Minimum Typical 51 51 25 7 Maximum 4 Units pF K K pF
ICS87949I
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); Output Impedance
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0, QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDx + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87949I
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VDD Outputs, VDDx Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.6 3.6 85 Units V V mA
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol VIH VIL VPP VCMR IIN VOH Parameter Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Input Current Output High Voltage IOH = -20mA 2.5 0.4 Test Conditions Minimum 2 -0.3 0.3 VDD - 2.0V Typical Maximum VDD + 0.3 0.8 1 VDD - 0.6V 120 Units V V V V A V V
VOL Output Low Voltage IOL = 20mA NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
Test Conditions PCLK, nPCLK CLK0, CLK1 PCLK, nPCLK CLK0, CLK1 Measured on rising edge at VDDx/2 PCLK, nPCLK CLK0, CLK1 Measured on rising edge at VDDx/2 Minimum 160 1.9 1.7 1.8 1.6 9.0 10.6 8.6 10.5 350 2.75 4 Typical Maximum Units MHz ns ns ns ns ps ns ns ns ns ns ns
ICS87949I
TABLE 5. AC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5
tsk(o) tsk(pp)
tR
Output Rise Time; 0.8 to 2.0V 0.1 1.0 NOTE 4 Output Fall Time; tF 0.8 to 2.0V 0.1 1.0 NOTE 4 Output Enable Time; tPZL, tPZH 11 NOTE 4 Output Disable Time; tPLZ, tPHZ 11 NOTE 4 NOTE 1: Measured from the VDD/2 or crosspoint of the input to VDDx/2 of the output. NOTE 2: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
ICS87949I
PARAMETER MEASUREMENT INFORMATION
VDD, VDDx = 1.65V0.15V
V DD
SCOPE
nPCLK
LVCMOS
Qx
PCLK
V
PP
Cross Points
V
CMR
GND = -1.65V0.15V
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
Qx
DDx
2
PART 1 Qx
V
DDx
2
V
Qy
DD x
2 tsk(o)
PART 2 Qy
V
DD x 2 tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
2.0V
2.0V V
SW I N G
0.8V Clock Outputs t
R
0.8V t
F
CLK0, CLK1 nPCLK
VDDx 2
OUTPUT RISE/FALL TIME
V QAx, QBx, QCx, QDx
DDx
PCLK
2 Pulse Width t
PERIOD
QAx, QBx, QCx, QDx
VDDx 2
odc =
t PW t PERIOD
odc & tPERIOD
87949AYI
PROPAGATION DELAY
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REV. B NOVEMBER 21, 2002
tPD
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR RELIABILITY INFORMATION
ICS87949I
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949I is: 1545
87949AYI
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7
REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
ICS87949I
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b b1 D D1 E E1 e ccc ddd 0.45 --0.05 1.35 0.22 0.22 BCC MINIMUM NOMINAL 52 --1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC --0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87949AYI
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8
REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
Marking ICS87949AYI ICS87949AYI Package 52 Lead LQFP 52 Lead LQFP on Tape and Reel Count 160 per tray 500 Temperature -40C to 85C -40C to 85C
ICS87949I
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87949AYI ICS87949AYIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87949AYI
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REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change In Features section revised bullet to read "Maximum output frequency..." instead of "Maximum input frequency...". In Pin Description Table revised MR/nOE description. Revised Output Rise & Fall Time Diagram. AC Characteristics table - corrected Output Enable/Disable Time symbols. DC Characteristics table - changed VCMR from GND + 1.5V min./VDD max. to VDD - 2.0V min./VDD - 0.6V max. AC Characteristics table - changed (PCLK, nPCLK) tpLH from 4.7ns max. to 9.0ns max.,deleted typical value. (CLK0, CLK1)) tpLH from 5.7ns max. to 10.6ns max., deleted typical value. (PCLK, nPCLK) tpHL from 4.6ns max. to 8.6ns max., deleted typical value. (CLK0, CLK1)) tpHL from 5.6ns max. to 10.5ns max., deleted typical value. Modified Package Outline to correspond with the Package Dimensions table. Date
ICS87949I
Rev
Table
Page 1 2 7 5 4 5
A
T1 T5 T4B T5
08/14/02
A
10/18/02
B
10/22/02
B
8
11/21/02
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REV. B NOVEMBER 21, 2002

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